1. Field of the Invention
This invention generally relates to a lead frame package.
2. Description of the Related Art
Lead frame packages have been widely used for a long time in the IC packaging field due to their low manufacturing cost and high reliability. However, as integrated circuit products are becoming faster in speed and smaller in volume, the traditional lead frame packages have been gradually obsolete for some high-efficiency integrated circuit products. Accordingly, ball grid array (BGA) packages and chip scale packages (CSP) have become popular packaging choices. The ball grid array (BGA) packages have been widely used in IC chips having high I/O count and requiring good electrical and thermal efficiencies, e.g. CPU chips and graphic chips. In addition, the chip scale packages (CSP) have been widely used in mobile products; the footprint size, package profile and package weight are major concerns for the chip scale packages (CSP).
However, the lead frame packages still remain their market share since they can provide a cost-effective solution for IC chips having low I/O count. The traditional lead frame packages are not capable of providing a solution for chip scale and low profile packages due to their long inner leads and outer leads. Therefore, the semiconductor packaging industry has developed a leadless package having no outer leads such that the footprint size and the package profile can be greatly reduced.
FIG. 1 shows a cross-sectional view of a leadless package 10, which comprises a plurality of inner leads 11a, a die pad 11b and a chip 12. The inner leads 11a are disposed at the bottom of the leadless package 10 as compared to the conventional gull-wing or J-leaded type package. The die pad 11b is exposed out of the bottom of the leadless package 10 so as to provide a better heat dissipation efficiency. The chip 12 is attached to the die pad 11b by silver epoxy and electrically connected to the plurality of inner leads 11a. 
Due to the elimination of the outer leads, the leadless package 10 has the features of low profile and light weight. Furthermore, the length reduction of the lead can also reduce the resistance, conductance and capacitance such that the leadless package 10 is suitably used in RF (radio-frequency) packages operating in several GHz to tens of GHz. Due to the use of existing BOM (bill of materials), the leadless package is a cost-effective package. All the above-mentioned properties make the leadless packages very suitable for use in telecommunication products (e.g. cellular phones), portable products (e.g. personal digital assistant (PDA)), digital cameras, and information appliance (IA).
Typically, the leadless package 10 is mounted on a substrate 16, e.g. a printed circuit board, by conventional surface mount technology (SMT). More specifically, the inner leads 11a exposed out of the bottom of the leadless package 10 are respectively bonded to a plurality of corresponding pads 18, formed on the printed circuit board 16, by solder 14. In the conventional surface mount technology (SMT) for mounting the leadless package 10 to the substrate 16, there exists a problem that the area of the inner leads 11a exposed out of the bottom of the leadless package 10 is too small and therefore causes poor solder connection and poor reliability. Although the solder fillet height can be increased by increasing the thickness of the leads 11a, the thickness of the leads 11a may be generally limited to around 0.15 mm due to the low profile of the leadless package. As shown in FIG. 1, the height of the inner lead 11a exposed out of the side wall of the package 10 is only about 0.15 mm for solder connection such that the solder connection is not solid enough.